Yuan Zhou


Email: yazhom@amazon.com

About Me

I just received my Ph.D. in ECE from Cornell University. My dissertation is advised by Prof. Zhiru Zhang in the Computer Systems Laboratory (CSL) at Cornell University. My Ph.D. research focuses on applying machine learning techniques to electronic design automation (EDA). I also worked on memory optimization, benchmarking, as well as performance and area optimization for HLS. I joined AWS AI as an Applied Scientist in May 2021.


Y. Zhou, Trace-Based Learning for Agile Hardware Design and Design Automation


Y. Zhou, H. Wang, J. Yin, and Z. Zhang, Distilling Arbitration Logic from Traces using Machine Learning: A Case Study on NoC, to appear in Design Automation Conference (DAC), Dec. 2021.

Y. Zhou, H. Ren, Y. Zhang, B. Keller, B. Khailany, and Z. Zhang, PRIMAL: Power Inference using Machine Learning, Design Automation Conference (DAC), Jun. 2019

Y. Zhou, U. Gupta, S. Dai, R. Zhao, N. Srivastava, H. Jin, J. Featherston, Y.-H. Lai, G. Liu, G. Velasquez, W. Wang, and Z. Zhang, Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs, International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2018. github

Y. Zhou, K. Al-Hawaj, and Z. Zhang, A New Approach to Automatic Memory Banking using Trace-Based Address Mining, International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2017.

W. Hua, Y. Zhou, C. De Sa, Z. Zhang, and G. E. Suh, Channel Gating Neural Networks, Thirty-third Conference on Neural Information Processing Systems (NeurIPS), Dec. 2019. github

W. Hua, Y. Zhou, C. De Sa, Z. Zhang, and G. E. Suh, Boosting the Performance of CNN Accelerators with Dynamic Fine-Grained Channel Gating, International Symposium on Microarchitecture (MICRO), Oct. 2019.

S. Dai, Y. Zhou, H. Zhang, E. Ustun, E. F.Y. Young, and Z. Zhang, Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning, International Symposium on Field-Programmable Custom Computing Machines (FCCM), Apr./May 2018. (Best Paper Award, short paper category) github

Y.-H. Lai, Y. Chi, Y. Hu, J. Wang, C. H. Yu, Y. Zhou, J. Cong, and Z. Zhang, HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing, International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2019. (Best Paper Award) github

E. Singh, F. Lonsing, S. Chattopadhyay, M. Strange, P. Wei, X. Zhang, Y. Zhou, J. Cong, D. Chen, Z. Zhang, P. Raina, C. Barrett, and S. Mitra, A-QED Verification of Hardware Accelerators, Design Automation Conference (DAC), Jul. 2020.