Office: 471E Rhodes Hall, Ithaca, NY 14850
I am a Ph.D candidate advised by Prof. Zhiru Zhang in Computer Systems Laboratory (CSL) at Cornell University. During summer 2018, I did an internship at NVIDIA research in Santa Clara, CA. I received my bachelor degree from the Department of Electronic Engineering at Tsinghua Univerisity in 2015.
My current research focuses on applying machine learning techniques to electronic design automation (EDA). More specifically, I am working on using machine learning to improve the power analysis and optimization flow. I am also broadly interested in hardware acceleration of machine learning and graph algorithms. I also worked on memory optimization, benchmarking, as well as performance and area optimization for HLS.
Y. Zhou, H. Ren, Y. Zhang, B. Keller, B. Khailany, and Z. Zhang, PRIMAL: Power Inference using Machine Learning, Design Automation Conference (DAC), Jun. 2019
Y. Zhou, U. Gupta, S. Dai, R. Zhao, N. Srivastava, H. Jin, J. Featherston, Y.-H. Lai, G. Liu, G. Velasquez, W. Wang, and Z. Zhang, Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs, International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2018.
Y. Zhou, K. Al-Hawaj, and Z. Zhang, A New Approach to Automatic Memory Banking using Trace-Based Address Mining, International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2017.
W. Hua, Y. Zhou, C. De Sa, Z. Zhang, and G. E. Suh, Channel Gating Neural Networks, to appear in Thirty-third Conference on Neural Information Processing Systems (NeurIPS), Dec. 2019.
W. Hua, Y. Zhou, C. De Sa, Z. Zhang, and G. E. Suh, Boosting the Performance of CNN Accelerators with Dynamic Fine-Grained Channel Gating, to appear in International Symposium on Microarchitecture (MICRO), Oct. 2019.
S. Dai, Y. Zhou, H. Zhang, E. Ustun, E. F.Y. Young, and Z. Zhang, Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning, International Symposium on Field-Programmable Custom Computing Machines (FCCM), Apr./May 2018. (Best Paper Award, short paper category)
Y.-H. Lai, Y. Chi, Y. Hu, J. Wang, C. H. Yu, Y. Zhou, J. Cong, and Z. Zhang, HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing, International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2019. (Best Paper Award)